1. Field of the Invention
This application is directed to delay-locked loops.
2. Description of the Related Art
High speed memory interfaces employ delay lines to position data with respect to clock or clocks with respect to data to meet system timing requirements. A delay line typically includes a series of delay cells, where the delay through each cell can be varied. Delay lines can be configured in a delay-locked loop (DLL), which automatically adjusts the voltage/current in the delay cell, so that the total delay of the delay line tracks the frequency of a reference signal supplied to the DLL. When the delay line supplies an output signal having the desired frequency and phase, the DLL is said to be locked.
High accuracy may be required for high speed memory interfaces. In typical computer systems, low power modes are used to save power and/or adjust operation of the computer to system processing and power requirements. In some prior art solutions, a DLL is provided for a number of delay lines and the control voltage/current that determines the delay of the delays cells is also applied to the delay cells of the associated delay lines. When a DRAM controller utilizing a delay line to position data and/or clocks enters a low power mode, the control voltage/current that determines the delay line delay must be frozen in place, as the DLL loses the reference clock. However, a frozen DLL cannot continue to compensate for temperature variations. If the memory controller is in a low power state for a long time, the temperature can change significantly and the DLL effectively loses lock. In addition, in some power states, the clock frequency can be changed either up or down to accommodate system requirements. For example, when a processor is being lightly utilized, the clock speed may be reduced to save power. The delay line effectively loses lock if the reference clock changes frequency.
Normally the time available to achieve lock is large, e.g., on the order of 100 microseconds. However, the clock utilized as the reference clock for the memory interface can change frequency by as much as 2×. That change occurs while the chip (DRAM) is in self-refresh mode. After any such change, the DLL needs to relock to the new frequency quickly, e.g., in about 2 microseconds, without sacrificing accuracy. Some modes require the memory controller to enter and exit quite rapidly so that main memory is not taken offline for too long. Specifically, some systems with Unified Memory Architecture (UMA) have maximum isochronous latency requirements that would be violated waiting for the DLL to re-achieve lock in the absence of a faster lock time. In these systems the DLL is required to lock in about 2 microseconds.